Voltage Sampling Apparatus and Method

An apparatus includes a first sampling switch coupled between a first voltage bus and a sampling capacitor, a first clock generator configured to produce a first gate drive signal fed into a gate of the first sampling switch, the first clock generator comprising a first capacitive coupled clock shifter, a first reset circuit and a second reset circuit, a second sampling switch coupled between a second voltage bus and the sampling capacitor, and a second clock generator configured to produce a second gate drive signal fed into a gate of the second sampling switch, the second clock generator comprising a second capacitive coupled clock shifter, a third reset circuit and a fourth reset circuit.