Voltage balancing circuit

A voltage balancing circuit includes (n-1)-number of voltage stabilization circuits (72, 73, 74) configured between k-th reference nodes of n-number of groups of resistances and k-th output nodes of the n-number of groups of main circuit capacitors (C1, C2, C3, C4) respectively where 2¤k¤n. The k-th voltage stabilization circuit (72, 73, 74) is configured in such a manner that the first transistor (Tr1, Tr3, Tr5) is connected via a first resistance (R4, R6, R10) to a (k-a)-th output node (N1) serving as the source node and the second transistor (Tr2, Tr4, Tr6) is connected via a second resistance (R5, R7, R11) further connected to a (k+b)-th output node N2) serving as the destination node, where 2¤k¤n, 1¤a¤k-1 and 1¤b¤n+1-k.