Intel aims advanced Xeon 6+ at AI edge computing

At the Mobile World Conference show in Barcelona, Intel showcased its most advanced processor yet, the Xeon 6+ processor, codenamed “Clearwater Forest.”

Technically, it is one of Intel’s most complex chiplet designs, with a package that combines a total of 12 compute chiplets manufactured on a mix of Intel 18A node, Intel 7, and Intel 3 manufacturing processes.

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Clearwater Forest supports the existing Xeon server platform socket, 12 memory channels, 96 PCIe 5.0 lanes, and 64 CXL 2.0 lanes. It supports memory up to DDR5-8000.The chip contains 288 E-cores, for Efficiency, with a high-bandwidth on-chip fabric to link two chips in a two-socket design.

One of the primary target markets is cloud providers has dozens if not hundreds of virtual machines can be spun up on a single processor. But also, Intel is targeting network environments through the Radio Access Network (RAN), 5G Core, and edge, while maintaining efficiency, openness, and cost control.

In a blog post announcing the Xeon 6+, Kevork Kechichian, executive vice president and general manager of the Data Center Group says this approach enables real-time inference inside virtualized RAN deployments, so data can be processed where it resides rather than moving it around.

Intel has an existing partnership with telecom giant Ericsson, and the two firms announced they have extended it to cover the joint development and marketing of what they call AI-native 6G solutions.

Details were scarce; the collaboration is described as advancing “future high-performance, and energy-efficient compute architectures designed for both AI for networks and Networks for AI.”

AI-native 6G will combine intelligent and programmable networks with advanced compute and real-time sensing. Over time, that evolution could bring sensing and compute closer together across the network.

So the two firms are not targeting one particular segment of the market, but the whole thing: connectivity, cloud, security, and compute capabilities for the RAN and packet core.

The intended outcome is an architecture “that combines intelligent, programmable networks with advanced compute and real-time sensing, which will underpin more responsive, efficient and capable services, and ultimately result in closer integration between sensing and compute.”

According to Intel, the Xeon 6+ series is planned for launch in the first-half 2026.

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