{
  "$type": "site.standard.document",
  "description": "An electrode arrangement (100; 200) comprises: a semiconductor carrier substrate (102; 202) having a first (104; 204) and a second side surface (106; 206); a first array of electrodes (110; 210) arranged above the first side surface (104; 204); a second array of electrodes (120; 220) arranged below…",
  "path": "/patents/1409855",
  "publishedAt": "2023-08-23T00:00:00.000Z",
  "site": "at://did:plc:oql6ds5vnff4ugar6rruliwd/site.standard.publication/3mn3ohu7oxx5w",
  "tags": [
    "A61B5/263",
    "IMEC VZW [BE]"
  ],
  "textContent": "An electrode arrangement (100; 200) comprises: a semiconductor carrier substrate (102; 202) having a first (104; 204) and a second side surface (106; 206); a first array of electrodes (110; 210) arranged above the first side surface (104; 204); a second array of electrodes (120; 220) arranged below the second side surface (106; 206); an electronic circuitry (130; 230) for processing electrical signals recorded by the electrodes (110, 120; 210, 220); a connecting layer (140 240) arranged above the electronic circuitry (130; 230) and providing a first connection (142a; 242a) between a first point (144a; 244a) and a second point (144b; 244b); a first interconnect (146; 246) for electrically connecting the first point (144a; 244a) to the electronic circuitry (130; 230); a second interconnect (148; 248) and a first through-substrate via (150; 250) which electrically connect the second point (144b; 244b) to the electrode (120; 220) in the second array.",
  "title": "AN ELECTRODE ARRANGEMENT, A NEURAL PROBE, AND A METHOD FOR MANUFACTURING AN ELECTRODE ARRANGEMENT"
}