{
  "$type": "site.standard.document",
  "description": "A microcontroller includes a plurality of (Intellectual Property) IP blocks each configured to perform one or more functions; a hardware power estimator circuit for estimating power of the microcontroller, the hardware power estimator including a hardware artificial neural network inlcuding a…",
  "path": "/patents/1359117",
  "publishedAt": "2024-02-08T00:00:00.000Z",
  "site": "at://did:plc:oql6ds5vnff4ugar6rruliwd/site.standard.publication/3mn3ohu7oxx5w",
  "tags": [
    "H02J3/003",
    "Infineon Technologies AG"
  ],
  "textContent": "A microcontroller includes a plurality of (Intellectual Property) IP blocks each configured to perform one or more functions; a hardware power estimator circuit for estimating power of the microcontroller, the hardware power estimator including a hardware artificial neural network inlcuding a plurality of interconnected nodes arranged in one or more stages, wherein each individual stage comprises: a first input layer including values indicating activities of the microcontroller and/or indicating active cells of the microcontroller; a second input layer including a weighted set of values; an output layer including values calculated for the individual node stage; and at least one intermediate layer situated between the input layer and the output layer, wherein each node of the at least one intermediate layer comprises a multiply and adder (MADD) circuit that is configured to calculate a value for the respective node using values received from the first and second input layers.",
  "title": "SYSTEMS, DEVICES AND METHODS FOR POWER MANAGEMENT AND POWER ESTIMATION"
}