{
  "$type": "site.standard.document",
  "description": "Aspects of the disclosure include a symmetric direct current (DC) link capacitor having a low parasitic equivalent series L-inductance (ESL). An exemplary capacitor can include one or more positive-dielectric-negative (PDN) stacks having a positive layer, a negative layer, and a dielectric layer…",
  "path": "/patents/1370710",
  "publishedAt": "2024-10-31T00:00:00.000Z",
  "site": "at://did:plc:oql6ds5vnff4ugar6rruliwd/site.standard.publication/3mn3ohu7oxx5w",
  "tags": [
    "H01G4/30",
    "GM GLOBAL TECHNOLOGY OPERATIONS LLC"
  ],
  "textContent": "Aspects of the disclosure include a symmetric direct current (DC) link capacitor having a low parasitic equivalent series L-inductance (ESL). An exemplary capacitor can include one or more positive-dielectric-negative (PDN) stacks having a positive layer, a negative layer, and a dielectric layer between the positive layer and the negative layer. A first contact layer is electrically coupled to the positive layer on a sidewall of the one or more PDN stacks and a second contact layer is electrically coupled to the negative layer on the sidewall of the one or more PDN stacks. A positive terminal is electrically coupled to the first contact layer and a negative terminal is electrically coupled to the second contact layer.",
  "title": "LOW PARASITIC EQUIVALENT SERIES L-INDUCTANCE (ESL) SYMMETRIC DIRECT CURRENT (DC) LINK CAPACITOR"
}