Operation circuit and chip

An operation circuit and a chip pertaining to the field of integrated circuit design technology are disclosed by the present invention. The circuit includes a capacitor charging/discharging module and an error amplification module electrically connected to the capacitor charging/discharging module. The capacitor charging/discharging module is configured to receive first, second and third signals external to the capacitor charging/discharging module, and to output a reference signal and a feedback signal. The error amplification module is configured to receive the reference and feedback signals and output a target signal to the capacitor charging/discharging module based on the received reference and feedback signals. The first, second and third signals are all analog signals, and in a steady state, values of the target, first, second and third signals satisfy a predefined mathematical relationship.