POWER-FAIL RETAINING CIRCUIT, METHOD AND POWER SUPPLY SYSTEM

The present invention provides a hold-up time circuit, a hold-up time method, and a power supply system. The circuit includes an energy storage capacitor, a step-down circuit and a step-up circuit. A first input end and a second input end of the step-down circuit are separately connected to two electrodes of an input power supply. A first output end and a second output end of the step-down circuit are separately connected to two electrodes of the energy storage capacitor. When the input power supply is normal, the step-down circuit is configured to perform reduction processing on an input voltage of the input power supply, and the energy storage capacitor is charged by an output of the step-down circuit. A first input end and a second input end of the step-up circuit are separately connected to the two electrodes of the energy storage capacitor. When the input power supply is power-off, the step-up circuit is configured to perform boost processing on an energy storage voltage of the energy storage capacitor. The energy storage capacitor is configured to: when the input power supply is normal, finish a charging process through an input voltage that has undergone reduction processing; and when the input power supply is power-off, supply power to an output load through an energy storage voltage that has undergone boost processing. In this embodiment, a long power-off protecting time is achieved when a low voltage is input.