GLOBALLY IRREGULAR POWER GRID

A method is described for determining power grid density on an integrated circuit. The method includes determining an initial placement of power switches, logic circuits, the power grid, and the logic grid. The method creates tiles covering the entire integrated circuit and assigns a power grid density and a logic grid density for each tile. Power losses are simulated for the entire chip and chip timing function is simulated. Based on the simulated power losses and the simulated chip timing, the power grid density and the logic grid density are adjusted on a per tile basis. The assignment of power grid density and logic grid density and simulations are iterated until a cessation condition is met. After the cessation condition is met, a final chip simulation is performed and the final routing is determined.