Internal combustion engine controller

In an internal combustion engine controller 1, a clock trouble determination signal from a clock trouble determining circuit 14 that diagnoses any clock input trouble is transmitted in parallel with an abnormality diagnosis signal outputted from an abnormality diagnosing circuit and causes it to be inputted to a trouble/abnormality signal output circuit 53, and the trouble/abnormality signal output circuit 53 achieves logical summing to output one line of resultant trouble/abnormality output OR signals to a microprocessor (MP) 3; 3A; 3B; 3C. The MP 3; 3A; 3B; 3C outputs to the trouble/abnormality signal output circuit 53 a trouble/abnormality confirmation input signal, and makes definite any of an abnormal state, a clock trouble state and a normal state based on the result of switching control of the status level of the pertinent trouble/abnormality output OR signal.