{
  "$type": "site.standard.document",
  "description": "A method for a clock monitoring subsystem of a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating is described. The method includes generating a set of clocks. The method also includes routing a selected one of the set of clocks for frequency measurement through one or more…",
  "path": "/patents/1375490",
  "publishedAt": "2025-05-15T00:00:00.000Z",
  "site": "at://did:plc:oql6ds5vnff4ugar6rruliwd/site.standard.publication/3mn3ohu7oxx5w",
  "tags": [
    "G06F1/08",
    "QUALCOMM Incorporated"
  ],
  "textContent": "A method for a clock monitoring subsystem of a system-on-chip (SoC) supporting dynamic clock scaling and voltage gating is described. The method includes generating a set of clocks. The method also includes routing a selected one of the set of clocks for frequency measurement through one or more clock routing subsystems. The method further includes adjusting a frequency of the selected clock after the selected clock is routed through the clock routing subsystems. The method also includes communicating a sideband signal to indicate the adjusted frequency of the selected clock.",
  "title": "CLOCK MONITORING SUBSYSTEM FOR SYSTEM-ON-CHIP SUPPORTING DYNAMIC CLOCK SCALING AND CLOCK GATING"
}