A parallel monitor circuit and semiconductor apparatus

A parallel monitor circuit (1A) for monitoring one (C1) of serially connected plural capacitors (Cn) receiving a direct recharging current is disclosed. The circuit comprises a bypassing transistor (Q1) for bypassing the capacitor (C1) with the recharging current when the capacitor voltage (VSo1) exceeds a monitor voltage (Vr1) determined by a voltage setting circuit in order to equally recharge the capacitors. A transferring unit transfers a voltage control circuit (VS1) and an internal circuit connected to the voltage control circuit to a standby mode when the voltage control circuit receives a specific combination of voltage codes (RC1).