{
  "$type": "site.standard.document",
  "description": "The monotonic counter is implemented as an integrated circuit where each counting bit (B1,B2,B3,B4) is provided by a memory cell (11) containing at least one memory element constituted of a resistor of polycrystalline silicon which is programmable by an irreversible decrease of its resistance. The…",
  "path": "/patents/1087394",
  "publishedAt": "2004-05-06T00:00:00.000Z",
  "site": "at://did:plc:oql6ds5vnff4ugar6rruliwd/site.standard.publication/3mn3ohu7oxx5w",
  "tags": [
    "G01C22/02",
    "ST MICROELECTRONICS SA [FR]"
  ],
  "textContent": "The monotonic counter is implemented as an integrated circuit where each counting bit (B1,B2,B3,B4) is provided by a memory cell (11) containing at least one memory element constituted of a resistor of polycrystalline silicon which is programmable by an irreversible decrease of its resistance. The counter also comprises a circuit (30) for decoding the states of memory cells for obtaining the resultant count. The programming of the resistor of polycrystalline silicon is by a temporary passage of a constraint current which is higher than a current for which the resistance has the maximum value. Each counting cell comprises a programming resistor connected between a first supply terminal and a differential read terminal, and at least one programming interrupter connecting the read terminal to a second supply terminal. The programming resistor is in the form of two resistors of polycrystalline silicon which are identical in size and doping level. The counter also comprises a circuit for programming control (CTRL) of each counting cell and for providing control signals to each programming interrupter. The four bits (B1,B2,B3,B4) are arranged in a line of cells (11) which are all read simultaneously for obtaining the outputs (S1,S2,S3,S4). The number of cells in the state 0 and the state 1 is detected by the decoding circuit (30) which has five counting outputs (C0,C1,C2,C3,C4) linked to the four inputs by a NAND gate (31), nine AND gates (32,33,34,35,36,37,38,39,40), two OR gates (41,42), and a NOR gate (43).",
  "title": "Monotonous counter based on memory cells"
}