{
  "$type": "site.standard.document",
  "bskyPostRef": {
    "cid": "bafyreiaslf6gxzopaok3qj4c2lppezgbkvfsgvfaruaxf7tgdao3gmww7i",
    "uri": "at://did:plc:oldu4osfqstkn27t4qzsrgtf/app.bsky.feed.post/3mlw2zurv6vb2"
  },
  "coverImage": {
    "$type": "blob",
    "ref": {
      "$link": "bafkreieahpy4oilgi2peb56xr4tfspyss3tyfmbzyybg7p4btojix25psq"
    },
    "mimeType": "image/png",
    "size": 111628
  },
  "path": "/gdevic/FPGA-Calculator",
  "publishedAt": "2026-05-15T17:15:58.000Z",
  "site": "https://github.com",
  "tags": [
    "Comments"
  ],
  "textContent": "Comments",
  "title": "I designed a nibble-oriented CPU in Verilog to build a scientific calculator"
}