{
"$type": "site.standard.document",
"bskyPostRef": {
"cid": "bafyreibne423mq3agxphza2oc4f4bmxvsfdb3urkfce4ektra5qquiyig4",
"uri": "at://did:plc:oldu4osfqstkn27t4qzsrgtf/app.bsky.feed.post/3mi6afespzt42"
},
"coverImage": {
"$type": "blob",
"ref": {
"$link": "bafkreiajcbgo24gcfdkopbxhdzzteazqhgobn3nzqgutfj5nlwid5z65za"
},
"mimeType": "image/png",
"size": 33379
},
"path": "/ben-j-c/verilog2factorio",
"publishedAt": "2026-03-26T10:47:36.000Z",
"site": "https://github.com",
"tags": [
"Comments"
],
"textContent": "Comments",
"title": "A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU)"
}