{
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  "path": "/syndications/kl-os-2025-12-27/",
  "publishedAt": "2025-12-27T00:00:00.000Z",
  "site": "https://scientiac.space",
  "tags": [
    "https://scientiac.space/syndications/kl-os-2025-12-27/POSSE",
    "Day 6"
  ],
  "textContent": "Day 6 was about Exceptions and handling those Exceptions in the kernel.\n\nIn RISC-V the CPU first checks `medeleg` register to determine which operation mode should handle the exception. In our case `U-mode/S-mode` is already handled by `OpenSBI`. Then, the CPU saves states into various `CSRs`. `stvec` register is set to `pc` then the exception is handled using the handler. Then `sret` is called to resume execution from the point where exception occurred.\n\nThe `handle_trap` function reads why the exception occurred and triggers the kernel panic. Which was implemented yesterday.",
  "title": "KL-OS: Exceptions",
  "updatedAt": "2026-04-22T08:40:35.724Z"
}