{
  "$type": "site.standard.document",
  "bskyPostRef": {
    "cid": "bafyreiebffoglqgaafq6gs3svdmxl4mpdj2atlldgkndnhu7xbxzi2iedm",
    "uri": "at://did:plc:ivbknywyskln22er3nkssdhl/app.bsky.feed.post/3mndavbxuhfh2"
  },
  "path": "/t/include-racy-reads-in-rust-memory-model-with-maybeinvalid-t/24289?page=3#post_49",
  "publishedAt": "2026-06-02T15:28:34.000Z",
  "site": "https://internals.rust-lang.org",
  "textContent": "ProgramCrafter:\n\n> Though I do like the bytewise-atomic memcpy more than this justification. (If only it was defined behavior on hardware specification side...)\n\nAtomic bytewise memcpy (in its most restricted form, that is still sufficient for SeqLocks) does not require mixed-size accesses, so there's no problem from the hardware side.",
  "title": "Include racy reads in Rust memory model with `MaybeInvalid<T>`"
}